[all-commits] [llvm/llvm-project] 2ebd63: [mlir][AMDGPU] Add packed 8-bit float conversion o...
Krzysztof Drewniak via All-commits
all-commits at lists.llvm.org
Thu Sep 28 07:44:30 PDT 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 2ebd633f145615a42d7e8b1d07cbdad294c244aa
https://github.com/llvm/llvm-project/commit/2ebd633f145615a42d7e8b1d07cbdad294c244aa
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2023-09-28 (Thu, 28 Sep 2023)
Changed paths:
A mlir/include/mlir/Conversion/ArithToAMDGPU/ArithToAMDGPU.h
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
A mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
A mlir/lib/Conversion/ArithToAMDGPU/CMakeLists.txt
M mlir/lib/Conversion/CMakeLists.txt
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
A mlir/test/Conversion/AMDGPUToROCDL/8-bit-floats.mlir
A mlir/test/Conversion/ArithToAMDGPU/8-bit-floats.mlir
M mlir/test/Dialect/AMDGPU/invalid.mlir
M mlir/test/Dialect/AMDGPU/ops.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[mlir][AMDGPU] Add packed 8-bit float conversion ops and lowering
Define operations that wrap the gfx940's new operations for converting
between f32 and registers containing packed sets of four 8-bit floats.
Define rocdl operations for the intrinsics and an AMDGPU dialect
wrapper around them (to account for the fact that MLIR distinguishes
the two float formats at the type level but that the LLVM IR does
not).
Define an ArithToAMDGPU pass, meant to run before conversion to LLVM,
that replaces relevant calls to arith.extf and arith.truncf with the
packed operations in the AMDGPU dialect. Note that the conversion
currently only handles scalars and vectors of rank <= 1, as we do not
have a usecase for multi-dimensional vector support right now.
Reviewed By: jsjodin
Differential Revision: https://reviews.llvm.org/D152457
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