[all-commits] [llvm/llvm-project] 8c07d5: [mlir][vector] don't emit non-rank 1 masked load a...

[Cullen Rhodes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8c07d5ec6d4b7c3fe66d2c45630d0a0741b5854d
      https://github.com/llvm/llvm-project/commit/8c07d5ec6d4b7c3fe66d2c45630d0a0741b5854d
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2023-09-28 (Thu, 28 Sep 2023)

  Changed paths:
    M mlir/lib/Dialect/Vector/Transforms/LowerVectorTransfer.cpp
    M mlir/test/Dialect/Vector/vector-transfer-to-vector-load-store.mlir

  Log Message:
  -----------
  [mlir][vector] don't emit non-rank 1 masked load and store (#67656)

The following patterns

  - TransferReadToVectorLoadLowering
  - TransferWriteToVectorStoreLowering

attempt to generate invalid vector.maskedload and vector.maskedstore ops
for non rank-1 vector types. These ops operate on 1-D vectors. This
patch adds a check to prevent this.