[all-commits] [llvm/llvm-project] 140a09: [AArch64][GlobalISel] More type support for G_VECR...

[chuongg3 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 140a094f5fe6090c61934850ef372cc868e7eeaf
      https://github.com/llvm/llvm-project/commit/140a094f5fe6090c61934850ef372cc868e7eeaf
  Author: chuongg3 <chuong.goh at arm.com>
  Date:   2023-09-28 (Thu, 28 Sep 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/aarch64-addv.ll
    M llvm/test/CodeGen/AArch64/vecreduce-add.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] More type support for G_VECREDUCE_ADD (#67433)

G_VECREDUCE_ADD is now able to have v4i16 and v8i8 vector types as
source registers