[all-commits] [llvm/llvm-project] 9816ed: [mlir][vector] add result type to vector.extract a...

[Cullen Rhodes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9816edc9f3ce198d41e364dd3467caa839a0c220
      https://github.com/llvm/llvm-project/commit/9816edc9f3ce198d41e364dd3467caa839a0c220
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2023-09-28 (Thu, 28 Sep 2023)

  Changed paths:
    M mlir/docs/Dialects/Vector.md
    M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
    M mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
    M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
    M mlir/lib/Dialect/Vector/Transforms/LowerVectorShapeCast.cpp
    M mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
    M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
    M mlir/test/Conversion/MathToFuncs/fpowi.mlir
    M mlir/test/Conversion/MathToFuncs/ipowi.mlir
    M mlir/test/Conversion/MathToLibm/convert-to-libm.mlir
    M mlir/test/Conversion/VectorToGPU/vector-to-mma-ops-mma-sync.mlir
    M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
    M mlir/test/Conversion/VectorToSCF/unrolled-tensor-transfer-ops.mlir
    M mlir/test/Conversion/VectorToSCF/unrolled-vector-to-loops.mlir
    M mlir/test/Conversion/VectorToSCF/vector-to-scf.mlir
    M mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir
    M mlir/test/Dialect/Arith/emulate-wide-int-very-wide.mlir
    M mlir/test/Dialect/Arith/emulate-wide-int.mlir
    M mlir/test/Dialect/Arith/int-narrowing.mlir
    M mlir/test/Dialect/Arith/test-emulate-wide-int-pass.mlir
    M mlir/test/Dialect/Linalg/transform-op-matmul-to-outerproduct.mlir
    M mlir/test/Dialect/Linalg/vectorize-convolution.mlir
    M mlir/test/Dialect/Math/canonicalize_ipowi.mlir
    M mlir/test/Dialect/NVGPU/transform-matmul-to-nvvm.mlir
    M mlir/test/Dialect/Vector/canonicalize.mlir
    M mlir/test/Dialect/Vector/constant-fold.mlir
    M mlir/test/Dialect/Vector/invalid.mlir
    M mlir/test/Dialect/Vector/ops.mlir
    M mlir/test/Dialect/Vector/scalar-vector-transfer-to-memref.mlir
    M mlir/test/Dialect/Vector/transform-vector.mlir
    M mlir/test/Dialect/Vector/vector-broadcast-lowering-transforms.mlir
    M mlir/test/Dialect/Vector/vector-contract-matvec-transforms.mlir
    M mlir/test/Dialect/Vector/vector-contract-to-dot-transforms.mlir
    M mlir/test/Dialect/Vector/vector-contract-to-matrix-intrinsics-transforms.mlir
    M mlir/test/Dialect/Vector/vector-contract-to-outerproduct-transforms.mlir
    M mlir/test/Dialect/Vector/vector-contract-to-parallel-arith-transforms.mlir
    M mlir/test/Dialect/Vector/vector-dropleadunitdim-transforms.mlir
    M mlir/test/Dialect/Vector/vector-extract-strided-slice-lowering.mlir
    M mlir/test/Dialect/Vector/vector-gather-lowering.mlir
    M mlir/test/Dialect/Vector/vector-multi-reduction-lowering.mlir
    M mlir/test/Dialect/Vector/vector-multi-reduction-outer-lowering.mlir
    M mlir/test/Dialect/Vector/vector-outerproduct-lowering-transforms.mlir
    M mlir/test/Dialect/Vector/vector-scan-transforms.mlir
    M mlir/test/Dialect/Vector/vector-shape-cast-lowering-scalable-vectors.mlir
    M mlir/test/Dialect/Vector/vector-shape-cast-lowering-transforms.mlir
    M mlir/test/Dialect/Vector/vector-transfer-to-vector-load-store.mlir
    M mlir/test/Dialect/Vector/vector-transforms.mlir
    M mlir/test/Dialect/Vector/vector-transpose-lowering.mlir
    M mlir/test/Dialect/Vector/vector-warp-distribute.mlir
    M mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-mma-2-4-f16.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/X86Vector/test-inline-asm-vector-avx512.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-3d.mlir

  Log Message:
  -----------
  [mlir][vector] add result type to vector.extract assembly format (#66499)

The vector.extract assembly format currently only contains the source
type, for example:

  %1 = vector.extract %0[1] : vector<3x7x8xf32>

it's not immediately obvious if this is the source or result type. This
patch improves the assembly format to make this clearer, so the above
becomes:

  %1 = vector.extract %0[1] : vector<7x8xf32> from vector<3x7x8xf32>