[all-commits] [llvm/llvm-project] ab89cf: [RISCV] Use vwsll.vi/vx + vwaddu.wv to lower vecto...

[Yeting Kuo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ab89cfd0f1ea7d825339e88f9fc703105c9a2193
      https://github.com/llvm/llvm-project/commit/ab89cfd0f1ea7d825339e88f9fc703105c9a2193
  Author: Yeting Kuo <46629943+yetingk at users.noreply.github.com>
  Date:   2023-09-28 (Thu, 28 Sep 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll

  Log Message:
  -----------
  [RISCV] Use vwsll.vi/vx + vwaddu.wv to lower vector.interleave when Zvbb enabled. (#67521)

The replacement could avoid an assignment to GPR when the type is vector
of i8/i16 and vwmaccu.wv which may have higher cost than vwsll.vi/vx.