[all-commits] [llvm/llvm-project] bd675f: [RISCV] Reduce LMUL when index is known when lower...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bd675f5899922764b167491d8caea8e2f547ab85
      https://github.com/llvm/llvm-project/commit/bd675f5899922764b167491d8caea8e2f547ab85
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-09-27 (Wed, 27 Sep 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

  Log Message:
  -----------
  [RISCV] Reduce LMUL when index is known when lowering insert_vector_elt (#66087)

Continuing on from #65997, if the index of insert_vector_elt is a
constant then we can work out what the minimum number of registers will
be needed for the slideup and choose a smaller type to operate on.

This reduces the LMUL for not just the slideup but also for the scalar
insert.