[all-commits] [llvm/llvm-project] aff6ff: [RISCV] Handle .vx pseudos in hasAllNBitUsers (#67...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aff6ffc8760b99cc3d66dd6e251a4f90040c0ab9
      https://github.com/llvm/llvm-project/commit/aff6ffc8760b99cc3d66dd6e251a4f90040c0ab9
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-09-27 (Wed, 27 Sep 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
    M llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll

  Log Message:
  -----------
  [RISCV] Handle .vx pseudos in hasAllNBitUsers (#67419)

Vector pseudos with scalar operands only use the lower SEW bits (or less
in the
case of shifts and clips). This patch accounts for this in
hasAllNBitUsers for
both SDNodes in RISCVISelDAGToDAG. We also need to handle this in
RISCVOptWInstrs otherwise we introduce slliw instructions that are less
compressible than their original slli counterpart.