[all-commits] [llvm/llvm-project] 435da4: [RISCV] Promote SETCC and VP_SETCC of f16 vectors ...

[Jianjian Guan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 435da4ef556812ae868a996c705b7dcc5ebc3705
      https://github.com/llvm/llvm-project/commit/435da4ef556812ae868a996c705b7dcc5ebc3705
  Author: Jianjian Guan <jacquesguan at me.com>
  Date:   2023-09-27 (Wed, 27 Sep 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll

  Log Message:
  -----------
  [RISCV] Promote SETCC and VP_SETCC of f16 vectors when only have zvfhmin (#66866)

This patch implements the promotion of fp16 vectors SETCC and VP_SETCC
when we only have zvfhmin but no zvfh.