[all-commits] [llvm/llvm-project] b26157: [RISCV] Correct Zhinx load/store patterns to use A...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b26157edf08184f2620b3df95048a97a1658c021
      https://github.com/llvm/llvm-project/commit/b26157edf08184f2620b3df95048a97a1658c021
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-09-26 (Tue, 26 Sep 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
    M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/half-intrinsics.ll
    M llvm/test/CodeGen/RISCV/half-mem.ll

  Log Message:
  -----------
  [RISCV] Correct Zhinx load/store patterns to use AddrRegImm.