[all-commits] [llvm/llvm-project] 0b3f9d: [flang]: This is to fix the HLFIR path for PPC Vec...

[Daniel Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0b3f9d8561226e3771db7f49dfb43d1301efc3c3
      https://github.com/llvm/llvm-project/commit/0b3f9d8561226e3771db7f49dfb43d1301efc3c3
  Author: Daniel Chen <cdchen at ca.ibm.com>
  Date:   2023-09-26 (Tue, 26 Sep 2023)

  Changed paths:
    M flang/include/flang/Optimizer/Dialect/FIRType.h
    M flang/lib/Lower/ConvertCall.cpp
    M flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp
    M flang/test/Lower/PowerPC/ppc-intrinsics.f90
    M flang/test/Lower/PowerPC/ppc-mma-accumulator-move-clear.f90
    M flang/test/Lower/PowerPC/ppc-mma-assemble-disassemble.f90
    M flang/test/Lower/PowerPC/ppc-mma-outer-product-1.f90
    M flang/test/Lower/PowerPC/ppc-mma-outer-product-2.f90
    M flang/test/Lower/PowerPC/ppc-pwr10-vec-intrinsics.f90
    A flang/test/Lower/PowerPC/ppc-vec-abs.f90
    A flang/test/Lower/PowerPC/ppc-vec-add-and-mul-sub-xor.f90
    A flang/test/Lower/PowerPC/ppc-vec-any.f90
    A flang/test/Lower/PowerPC/ppc-vec-cmp.f90
    M flang/test/Lower/PowerPC/ppc-vec-convert.f90
    A flang/test/Lower/PowerPC/ppc-vec-cvf-elem-order.f90
    M flang/test/Lower/PowerPC/ppc-vec-extract-elem-order.f90
    M flang/test/Lower/PowerPC/ppc-vec-extract.f90
    M flang/test/Lower/PowerPC/ppc-vec-insert-elem-order.f90
    M flang/test/Lower/PowerPC/ppc-vec-insert.f90
    M flang/test/Lower/PowerPC/ppc-vec-load-elem-order.f90
    M flang/test/Lower/PowerPC/ppc-vec-load.f90
    A flang/test/Lower/PowerPC/ppc-vec-max-min-madd-nmsub.f90
    M flang/test/Lower/PowerPC/ppc-vec-merge-elem-order.f90
    M flang/test/Lower/PowerPC/ppc-vec-merge.f90
    M flang/test/Lower/PowerPC/ppc-vec-perm-elem-order.f90
    M flang/test/Lower/PowerPC/ppc-vec-perm.f90
    A flang/test/Lower/PowerPC/ppc-vec-sel.f90
    M flang/test/Lower/PowerPC/ppc-vec-shift-be-le.f90
    M flang/test/Lower/PowerPC/ppc-vec-shift.f90
    M flang/test/Lower/PowerPC/ppc-vec-splat-elem-order.f90
    M flang/test/Lower/PowerPC/ppc-vec-splat.f90
    M flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90
    M flang/test/Lower/PowerPC/ppc-vec-store.f90
    R flang/test/Lower/PowerPC/ppc-vec_abs.f90
    R flang/test/Lower/PowerPC/ppc-vec_add-and-mul-sub-xor.f90
    R flang/test/Lower/PowerPC/ppc-vec_any.f90
    R flang/test/Lower/PowerPC/ppc-vec_cmp.f90
    R flang/test/Lower/PowerPC/ppc-vec_cvf-elem-order.f90
    R flang/test/Lower/PowerPC/ppc-vec_max-min-madd-nmsub.f90
    R flang/test/Lower/PowerPC/ppc-vec_sel.f90
    M flang/test/Lower/PowerPC/ppc-vector-types.f90

  Log Message:
  -----------
  [flang]: This is to fix the HLFIR path for PPC Vector type intrinsics. (#66547)

PowerPC Vector type intrinsics currently crashes with
`-flang-experimental-hlfir` is specified.

This patch is to fix the HLFIR path for PowerPC Vector type intrinsics.

The patch:
1. Added the `flang-experimental-hlfir` option to all PowerPC vector intrinsic testing.
2. Removed the FIR/MLIR testing to reduce the maintenance cost.
3. Fixed a few verification IR for some non-functional changes in LLVM IR in HLFIR path.