[all-commits] [llvm/llvm-project] de1738: [RISCV][GISel] Add RegBank selection for G_SMULH (...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: de17384c05146aa395607bde93b6c68bf6f42a8b
      https://github.com/llvm/llvm-project/commit/de17384c05146aa395607bde93b6c68bf6f42a8b
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2023-09-25 (Mon, 25 Sep 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul-ext.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul-ext.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir

  Log Message:
  -----------
  [RISCV][GISel] Add RegBank selection for G_SMULH (#67381)

Along with its missing tests in instruction selection and legalizer.