[all-commits] [llvm/llvm-project] 0d7c34: [RISCV][GISel] Add instruction selection for G_SEX...
Min-Yih Hsu via All-commits
all-commits at lists.llvm.org
Mon Sep 25 15:08:35 PDT 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 0d7c340c2cc89b71d398479c9adcac77f0336c6e
https://github.com/llvm/llvm-project/commit/0d7c340c2cc89b71d398479c9adcac77f0336c6e
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2023-09-25 (Mon, 25 Sep 2023)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/sext-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zext-rv64.mir
Log Message:
-----------
[RISCV][GISel] Add instruction selection for G_SEXT, G_ZEXT, and G_SEXT_INREG (#67359)
G_SEXT and G_ZEXT are supported via patterns imported from SDISel;
G_SEXT_INREG is selected using hand-written code as there is no
(functional) rule at this moment to import G_SEXT_INREG from
ISD::SEXT_INREG.
Credit helps from @topperc on G_SEXT and G_ZEXT.
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