[all-commits] [llvm/llvm-project] 671e2b: [NVPTX] Improve lowering of v2i16 logical ops. (#6...

[Artem Belevich via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 671e2ba45bf35a7c96a1a374c4956cce7e5d4d55
      https://github.com/llvm/llvm-project/commit/671e2ba45bf35a7c96a1a374c4956cce7e5d4d55
  Author: Artem Belevich <tra at google.com>
  Date:   2023-09-25 (Mon, 25 Sep 2023)

  Changed paths:
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
    M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
    M llvm/test/CodeGen/NVPTX/unfold-masked-merge-vector-variablemask.ll

  Log Message:
  -----------
  [NVPTX] Improve lowering of v2i16 logical ops. (#67365)

Bitwise logical ops can always be done as b32, regardless of
availability of other v2i16 ops, that would need a new GPU.

Includes the missing lowering for 2-argument register operation variants
and additional tests for `and`.