[all-commits] [llvm/llvm-project] c649fd: [MachineSink][AArch64] Sink instruction copies whe...

[Momchil Velikov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c649fd34e928ad01951cbff298c5c44853dd41dd
      https://github.com/llvm/llvm-project/commit/c649fd34e928ad01951cbff298c5c44853dd41dd
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2023-09-25 (Mon, 25 Sep 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetInstrInfo.h
    M llvm/include/llvm/CodeGen/TargetPassConfig.h
    M llvm/lib/CodeGen/ImplicitNullChecks.cpp
    M llvm/lib/CodeGen/MachineSink.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.h
    M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/test/CodeGen/AArch64/addsub-shifted-reg-cheap-as-move.ll
    M llvm/test/CodeGen/AArch64/align-down.ll
    M llvm/test/CodeGen/AArch64/and-mask-removal.ll
    M llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll
    M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
    M llvm/test/CodeGen/AArch64/arm64-long-shift.ll
    M llvm/test/CodeGen/AArch64/arm64-stp.ll
    M llvm/test/CodeGen/AArch64/arm64_32-addrs.ll
    M llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
    M llvm/test/CodeGen/AArch64/atomic-ops.ll
    M llvm/test/CodeGen/AArch64/cmp-select-sign.ll
    M llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
    M llvm/test/CodeGen/AArch64/loop-sink.mir
    M llvm/test/CodeGen/AArch64/nontemporal-load.ll
    M llvm/test/CodeGen/AArch64/optimize-imm.ll
    M llvm/test/CodeGen/AArch64/overeager_mla_fusing.ll
    M llvm/test/CodeGen/AArch64/rand.ll
    M llvm/test/CodeGen/AArch64/shrink-constant-multiple-users.ll
    M llvm/test/CodeGen/AArch64/sink-and-fold.ll
    M llvm/test/CodeGen/AArch64/swift-async-win.ll
    M llvm/test/CodeGen/AArch64/swift-async.ll

  Log Message:
  -----------
  [MachineSink][AArch64] Sink instruction copies when they can replace copy into hard register or folded into addressing mode

This patch adds a new code transformation to the `MachineSink` pass,
that tries to sink copies of an instruction, when the copies can be folded
into the addressing modes of load/store instructions, or
replace another instruction (currently, copies into a hard register).

The criteria for performing the transformation is that:
* the register pressure at the sink destination block must not
  exceed the register pressure limits
* the latency and throughput of the load/store or the copy must not deteriorate
* the original instruction must be deleted

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D152828