[all-commits] [llvm/llvm-project] 0a5d52: [RISCV][CostModel] Add getCFInstrCost RISC-V imple...

[Sergey Kachkov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0a5d52a757f389b4f7ee3ee1ad6840ff7ce33e51
      https://github.com/llvm/llvm-project/commit/0a5d52a757f389b4f7ee3ee1ad6840ff7ce33e51
  Author: Sergey Kachkov <109674256+skachkov-sc at users.noreply.github.com>
  Date:   2023-09-25 (Mon, 25 Sep 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    M llvm/test/Analysis/CostModel/RISCV/abs.ll
    M llvm/test/Analysis/CostModel/RISCV/active_lane_mask.ll
    M llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
    M llvm/test/Analysis/CostModel/RISCV/arith-int.ll
    M llvm/test/Analysis/CostModel/RISCV/cast.ll
    M llvm/test/Analysis/CostModel/RISCV/fca-load-store.ll
    M llvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll
    M llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll
    M llvm/test/Analysis/CostModel/RISCV/fp-min-max-abs.ll
    M llvm/test/Analysis/CostModel/RISCV/fp-sqrt-pow.ll
    M llvm/test/Analysis/CostModel/RISCV/fp-trig-log-exp.ll
    M llvm/test/Analysis/CostModel/RISCV/fround.ll
    M llvm/test/Analysis/CostModel/RISCV/gep-zero-indices.ll
    M llvm/test/Analysis/CostModel/RISCV/gep.ll
    M llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
    M llvm/test/Analysis/CostModel/RISCV/int-min-max.ll
    M llvm/test/Analysis/CostModel/RISCV/int-sat-math.ll
    M llvm/test/Analysis/CostModel/RISCV/logicalop.ll
    M llvm/test/Analysis/CostModel/RISCV/masked_ldst.ll
    M llvm/test/Analysis/CostModel/RISCV/phi-const.ll
    M llvm/test/Analysis/CostModel/RISCV/reduce-add.ll
    M llvm/test/Analysis/CostModel/RISCV/reduce-and.ll
    M llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll
    M llvm/test/Analysis/CostModel/RISCV/reduce-max.ll
    M llvm/test/Analysis/CostModel/RISCV/reduce-min.ll
    M llvm/test/Analysis/CostModel/RISCV/reduce-or.ll
    M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-fp.ll
    M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-int.ll
    M llvm/test/Analysis/CostModel/RISCV/reduce-xor.ll
    M llvm/test/Analysis/CostModel/RISCV/rvv-cmp.ll
    M llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll
    M llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll
    M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
    M llvm/test/Analysis/CostModel/RISCV/rvv-load-store.ll
    M llvm/test/Analysis/CostModel/RISCV/rvv-phi-const.ll
    M llvm/test/Analysis/CostModel/RISCV/rvv-select.ll
    M llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
    M llvm/test/Analysis/CostModel/RISCV/scalable-gather.ll
    M llvm/test/Analysis/CostModel/RISCV/scalable-scatter.ll
    M llvm/test/Analysis/CostModel/RISCV/shuffle-broadcast.ll
    M llvm/test/Analysis/CostModel/RISCV/shuffle-extract_subvector.ll
    M llvm/test/Analysis/CostModel/RISCV/shuffle-insert.ll
    M llvm/test/Analysis/CostModel/RISCV/shuffle-insert_subvector.ll
    M llvm/test/Analysis/CostModel/RISCV/shuffle-interleave.ll
    M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
    M llvm/test/Analysis/CostModel/RISCV/shuffle-reverse.ll
    M llvm/test/Analysis/CostModel/RISCV/shuffle-select.ll
    M llvm/test/Analysis/CostModel/RISCV/shuffle-transpose.ll
    M llvm/test/Analysis/CostModel/RISCV/splice.ll
    M llvm/test/Analysis/CostModel/RISCV/stepvector.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll

  Log Message:
  -----------
  [RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599)

This patch implements getCFInstrCost TTI hook that mostly affects
LoopVectorizer decisions. It sets zero cost for PHI nodes and zero
throughput cost for branches (assuming that branches are likely to
be predicted). The implementation is similar to X86/AArch64/PowerPC
targets and reduces loop cost by excluding induction PHIs/loop latch
branches, which in turn leads to selecting smaller vectorization
factor.