[all-commits] [llvm/llvm-project] 142efd: [AMDGPU] Add ISD::FSHR Handling to AMDGPUISD::PERM...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 142efd6d612965897cf0b9d560348bf40c15ebaa
      https://github.com/llvm/llvm-project/commit/142efd6d612965897cf0b9d560348bf40c15ebaa
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-09-24 (Sun, 24 Sep 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/permute_i8.ll

  Log Message:
  -----------
  [AMDGPU] Add ISD::FSHR Handling to AMDGPUISD::PERM matching

Pulled out of D159533, which encourages (zext (trunc x)) -> x folds, leading to more ISD::FSHR nodes, which was breaking some existing AMDGPUISD::PERM tests

Differential Revision: https://reviews.llvm.org/D159533


  Commit: 8b36d082c48c81454dcc66d9e70e473ae4b2b7f8
      https://github.com/llvm/llvm-project/commit/8b36d082c48c81454dcc66d9e70e473ae4b2b7f8
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-09-24 (Sun, 24 Sep 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/AMDGPU/ctpop16.ll
    M llvm/test/CodeGen/AMDGPU/permute_i8.ll

  Log Message:
  -----------
  [DAG] getNode() - fold (zext (trunc x)) -> x iff the upper bits are known zero - add SRL support

This is part of the work to address the D155472 regressions, there's a number of issues with generalizing this fold which is why I'm just adding SRL support atm.

Differential Revision: https://reviews.llvm.org/D159533


Compare: https://github.com/llvm/llvm-project/compare/4c241a9335c3...8b36d082c48c