[all-commits] [llvm/llvm-project] 6fbbcb: [TableGen] Fix ordering of register classes. (#67245)

[Ivan Kosarev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6fbbcb4ee724e23edd0fcd5b51877aff19dabd77
      https://github.com/llvm/llvm-project/commit/6fbbcb4ee724e23edd0fcd5b51877aff19dabd77
  Author: Ivan Kosarev <ivan.kosarev at amd.com>
  Date:   2023-09-24 (Sun, 24 Sep 2023)

  Changed paths:
    M llvm/utils/TableGen/CodeGenRegisters.cpp

  Log Message:
  -----------
  [TableGen] Fix ordering of register classes. (#67245)

This commit:

TableGen: Try to fix expensive checks failures
d2a9b87fee84766b28bd39b46c913da00e1450f4

fixed one of the sort() calls, but there's another.

Caught on expensive-checks buildbots that started to fail sporadically
after submitting

[AMDGPU] Add True16 register classes.
469b3bfad20550968ac428738eb1f8bb8ce3e96d