[all-commits] [llvm/llvm-project] 7cd01a: [RISCV][GISel] Add test showing missed opportunity...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7cd01afb73a2b88ab410404932ebdaf04becd883
      https://github.com/llvm/llvm-project/commit/7cd01afb73a2b88ab410404932ebdaf04becd883
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-09-22 (Fri, 22 Sep 2023)

  Changed paths:
    M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll

  Log Message:
  -----------
  [RISCV][GISel] Add test showing missed opportunity to use X0 for the LHS of sub for negate.

I had to disable the late copy propagation pass that can see through
the ADDI we were previously emitting. We really want to get this
in the register coalescer if not even earlier.


  Commit: 972df2ceccbafe0cc8d1a79d08533b623a5640ab
      https://github.com/llvm/llvm-project/commit/972df2ceccbafe0cc8d1a79d08533b623a5640ab
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-09-22 (Fri, 22 Sep 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir

  Log Message:
  -----------
  [RISCV][GISel] Emit G_CONSTANT 0 as a copy from X0. (#67202)

We need to use a COPY so the register coalescer can replace reads
of the register we copy to with X0. This is needed so that we use
X0 on instructions that don't have an immediate form.

This was reviewed as #67202.


Compare: https://github.com/llvm/llvm-project/compare/12ee3a6f53db...972df2ceccba