[all-commits] [llvm/llvm-project] 4b0df1: [VPlan] Fix invalid IR in unit test input, run ver...

[Florian Hahn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4b0df112daa1d967abeca1473c5e81e21d9af36a
      https://github.com/llvm/llvm-project/commit/4b0df112daa1d967abeca1473c5e81e21d9af36a
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2023-09-22 (Fri, 22 Sep 2023)

  Changed paths:
    M llvm/unittests/Transforms/Vectorize/VPlanSlpTest.cpp
    M llvm/unittests/Transforms/Vectorize/VPlanTestBase.h

  Log Message:
  -----------
  [VPlan] Fix invalid IR in unit test input, run verifier.

Some tests were passing invalid IR to the VPlan construction logic. Fix
the invalid IR and run the verifier on the input to avoid issues in the
future.