[all-commits] [llvm/llvm-project] ec5b0e: [RISCV] Truncate constants to eltwidth before chec...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ec5b0ef7d74e9112909037abacd3c2d708e588b8
      https://github.com/llvm/llvm-project/commit/ec5b0ef7d74e9112909037abacd3c2d708e588b8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-09-22 (Fri, 22 Sep 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

  Log Message:
  -----------
  [RISCV] Truncate constants to eltwidth before checking simm5 when con… (#67062)

…verting VMV_V_X to VMV_X_S.

Instruction selection knows the bits past EltWidth are ignored, we
should do the same here.