[all-commits] [llvm/llvm-project] 469b3b: [AMDGPU] Add True16 register classes.

[Ivan Kosarev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 469b3bfad20550968ac428738eb1f8bb8ce3e96d
      https://github.com/llvm/llvm-project/commit/469b3bfad20550968ac428738eb1f8bb8ce3e96d
  Author: Ivan Kosarev <ivan.kosarev at amd.com>
  Date:   2023-09-22 (Fri, 22 Sep 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
    M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
    M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
    M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
    M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
    M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
    M llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
    M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected

  Log Message:
  -----------
  [AMDGPU] Add True16 register classes.

Reviewed By: rampitec, Joe_Nash

Differential Revision: https://reviews.llvm.org/D156099