[all-commits] [llvm/llvm-project] b967f3: [AArch64] Separate PNR into its own Register Class...

[Matthew Devereau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b967f3a1d7d3be8180964001cff16ac8c22517e9
      https://github.com/llvm/llvm-project/commit/b967f3a1d7d3be8180964001cff16ac8c22517e9
  Author: Matthew Devereau <matthew.devereau at arm.com>
  Date:   2023-09-21 (Thu, 21 Sep 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
    A llvm/test/CodeGen/AArch64/PNRtoPPRCopy.mir
    M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
    M llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll
    M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
    M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
    M llvm/test/CodeGen/AArch64/preserve.ll
    M llvm/test/CodeGen/AArch64/spillfill-sve.mir
    M llvm/test/MC/AArch64/SVE/cntp-diagnostics.s

  Log Message:
  -----------
  [AArch64] Separate PNR into its own Register Class (#65306)

This patch separates PNR registers into their own register class instead
of sharing a register class with PPR registers. This primarily allows us
to return more accurate register classes when applying assembly
constraints, but also more protection from supplying an incorrect
predicate type to an invalid register operand.