[all-commits] [llvm/llvm-project] 0eb0a6: [AArch64] Correctly determine if {ADD, SUB}{W, X}rs ...

[Momchil Velikov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0eb0a65d0f9c5735c51b7816d68d3200f54b5a3e
      https://github.com/llvm/llvm-project/commit/0eb0a65d0f9c5735c51b7816d68d3200f54b5a3e
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2023-09-21 (Thu, 21 Sep 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    A llvm/test/CodeGen/AArch64/addsub-shifted-reg-cheap-as-move.ll

  Log Message:
  -----------
  [AArch64] Correctly determine if {ADD,SUB}{W,X}rs instructions are cheap

These are marked to be "as cheap as a move".

According to publicly available Software Optimization Guides, they
have one cycle latency and maximum throughput only on some
microarchitectures, only for `LSL` and only for some shift amounts.

This patch uses the subtarget feature `FeatureALULSLFast` to determine
how cheap the instructions are.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D152827

Change-Id: I8f0d7e79bcf277ebf959719991c29a1bc7829486