[all-commits] [llvm/llvm-project] b5ff71: [RISCV] Shrink vslideup's LMUL when lowering fixed...

Luke Lau via All-commits all-commits at lists.llvm.org
Thu Sep 21 05:56:02 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b5ff71e261b637ab7088fb5c3314bf71d6e01da7
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-09-21 (Thu, 21 Sep 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll

  Log Message:
  [RISCV] Shrink vslideup's LMUL when lowering fixed insert_subvector  (#65997)

Similar to #65598, if we're using a vslideup to insert a fixed length
vector into another vector, then we can work out the minimum number of
registers it will need to slide up across given the minimum VLEN, and
shrink the type operated on to reduce LMUL accordingly.

This is somewhat dependent on #66211 , since it introduces a subregister
copy that triggers a crash with -early-live-intervals in one of the

Stacked upon #66211

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