[all-commits] [llvm/llvm-project] 13e9a5: [RISCV] Add overlapping constraints label

[Piyou Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 13e9a56854c3a5ffddeafb8755facb74d2b74121
      https://github.com/llvm/llvm-project/commit/13e9a56854c3a5ffddeafb8755facb74d2b74121
  Author: Piyou Chen <piyou.chen at sifive.com>
  Date:   2023-09-21 (Thu, 21 Sep 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  Log Message:
  -----------
  [RISCV] Add overlapping constraints label

The RISCV-V-Spec[1] describes which RVV instructions are allowed to overlap between source operands and destination operands. Currently, most of these instructions are constrained with early-clobber.

This patch labels these instructions with TargetOverlapConstraintType in pseudo to indicate that these instructions can overlap.

The value of TargetOverlapConstraintType is:

1 -> default
2 -> narrow case
3 -> widen case

This information is useful for future optimization passes.

[1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#52-vector-operands

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D157588