[all-commits] [llvm/llvm-project] d7fab6: [lldb][AArch64] Add SME's streaming vector control...

[David Spickett via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d7fab666955e9ef0d456b6dfb737f5a18241c97c
      https://github.com/llvm/llvm-project/commit/d7fab666955e9ef0d456b6dfb737f5a18241c97c
  Author: David Spickett <david.spickett at linaro.org>
  Date:   2023-09-20 (Wed, 20 Sep 2023)

  Changed paths:
    M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
    M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
    M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
    M lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
    M lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
    M lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
    M lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py

  Log Message:
  -----------
  [lldb][AArch64] Add SME's streaming vector control register

Software can tell if it is in streaming SVE mode by checking
the Streaming Vector Control Register (SVCR).

"E3.1.9 SVCR, Streaming Vector Control Register" in
"Arm® Architecture Reference Manual Supplement, The Scalable Matrix
Extension (SME), for Armv9-A"

https://developer.arm.com/documentation/ddi0616/latest/

This is especially useful for debug because the names of the
SVE registers are the same betweeen non-streaming and streaming mode.

The Linux Kernel chose to not put this register behind ptrace,
and it can be read from EL0. However, this would mean running code
in process to read it. That can be done but we already know all
the information just from ptrace.

So this is a pseudo register that matches the architectural
content. The name is just "svcr", which aligns with GDB's proposed naming,
and it's added to the existing SME register set.

The SVCR register contains two bits:
0 : Whether streaming SVE mode is enabled (SM)
1 : Whether the array storage is enabled (ZA)

Array storage can be active when streaming mode is not, so this register
can have any permutation of those bits.

This register is currently read only. We can emulate the result of
writing to it, using ptrace. However at this point the utility of that
is not obvious.

Existing tests have been updated to check for appropriate SVCR values
at various points.

Given that this register is a read only pseudo, there is no need
to save and restore it around expressions.

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D154927