[all-commits] [llvm/llvm-project] 86b32c: [RISCV] Match strided load via DAG combine (#66800)

Philip Reames via All-commits all-commits at lists.llvm.org
Tue Sep 19 14:11:06 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 86b32c4b55b51dec1abb15680e8566f36fb7dbd9
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-09-19 (Tue, 19 Sep 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

  Log Message:
  [RISCV] Match strided load via DAG combine (#66800)

This change matches a masked.stride.load from a mgather node whose index
operand is a strided sequence. We can reuse the VID matching from
build_vector lowering for this purpose.

Note that this duplicates the matching done at IR by
RISCVGatherScatterLowering.cpp. Now that we can widen gathers to a wider
SEW, I don't see a good way to remove this duplication. The only obvious
alternative is to move thw widening transform to IR, but that's a no-go
as I want other DAGs to run first. I think we should just live with the
duplication - particularly since the reuse is isSimpleVIDSequence means
the duplication is somewhat minimal.

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