[all-commits] [llvm/llvm-project] e0919b: [CodeGen] Renumber slot indexes before register al...

Jay Foad via All-commits all-commits at lists.llvm.org
Tue Sep 19 03:26:41 PDT 2023 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e0919b189bf2df4f97f22ba40260ab5153988b14
      https://github.com/llvm/llvm-project/commit/e0919b189bf2df4f97f22ba40260ab5153988b14
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2023-09-19 (Tue, 19 Sep 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/SlotIndexes.h
    M llvm/lib/CodeGen/RegAllocGreedy.cpp
    M llvm/lib/CodeGen/SlotIndexes.cpp
    M llvm/test/CodeGen/AArch64/active_lane_mask.ll
    M llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
    M llvm/test/CodeGen/AArch64/arm64-cse.ll
    M llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
    M llvm/test/CodeGen/AArch64/extbinopload.ll
    M llvm/test/CodeGen/AArch64/faddp-half.ll
    M llvm/test/CodeGen/AArch64/fcvt_combine.ll
    M llvm/test/CodeGen/AArch64/fdiv.ll
    M llvm/test/CodeGen/AArch64/fpow.ll
    M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
    M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
    M llvm/test/CodeGen/AArch64/frem.ll
    M llvm/test/CodeGen/AArch64/llvm.exp10.ll
    M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
    M llvm/test/CodeGen/AArch64/neon-extadd.ll
    M llvm/test/CodeGen/AArch64/pow.ll
    M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
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    M llvm/test/CodeGen/AMDGPU/bswap.ll
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    M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
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    M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
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    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
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    M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
    M llvm/test/CodeGen/AMDGPU/mul.ll
    M llvm/test/CodeGen/AMDGPU/pr51516.mir
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    M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
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    M llvm/test/CodeGen/AMDGPU/sdiv.ll
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    M llvm/test/CodeGen/AMDGPU/select.f16.ll
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    M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
    M llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
    M llvm/test/CodeGen/AMDGPU/srem64.ll
    M llvm/test/CodeGen/AMDGPU/swdev373493.ll
    M llvm/test/CodeGen/AMDGPU/swdev380865.ll
    M llvm/test/CodeGen/AMDGPU/udiv.ll
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    M llvm/test/CodeGen/AMDGPU/wave32.ll
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    M llvm/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll
    M llvm/test/CodeGen/Hexagon/ntstbit.ll
    M llvm/test/CodeGen/Hexagon/signext-inreg.ll
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    M llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
    M llvm/test/CodeGen/PowerPC/sat-add.ll
    M llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
    M llvm/test/CodeGen/PowerPC/sub-of-not.ll
    M llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll
    M llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
    M llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/RISCV/branch-relaxation.ll
    M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
    M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/mul.ll
    M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
    M llvm/test/CodeGen/RISCV/push-pop-popret.ll
    M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
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    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
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    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
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    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
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    M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
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    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
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    M llvm/test/CodeGen/SPARC/smulo-128-legalisation-lowering.ll
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    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
    M llvm/test/CodeGen/X86/vector-lzcnt-512.ll
    M llvm/test/CodeGen/X86/vector-reduce-fmax.ll
    M llvm/test/CodeGen/X86/vector-reduce-fmaximum.ll
    M llvm/test/CodeGen/X86/vector-reduce-fmin.ll
    M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
    M llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll
    M llvm/test/CodeGen/X86/vector-shuffle-variable-128.ll
    M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
    M llvm/test/CodeGen/X86/vector-trunc-usat.ll
    M llvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll
    M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
    M llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
    M llvm/test/CodeGen/X86/x86-interleaved-access.ll
    M llvm/test/CodeGen/X86/xmulo.ll
    M llvm/test/Transforms/CodeGenPrepare/AArch64/large-offset-gep.ll

  Log Message:
  -----------
  [CodeGen] Renumber slot indexes before register allocation (#66334)

RegAllocGreedy uses SlotIndexes::getApproxInstrDistance to approximate
the length of a live range for its heuristics. Renumbering all slot
indexes with the default instruction distance ensures that this estimate
will be as accurate as possible, and will not depend on the history of
how instructions have been added to and removed from SlotIndexes's maps.

This also means that enabling -early-live-intervals, which runs the
SlotIndexes analysis earlier, will not cause large amounts of churn due
to different register allocator decisions.

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