[all-commits] [llvm/llvm-project] 17a12a: [RISCV] Add test case to show bad codegen for unal...

Craig Topper via All-commits all-commits at lists.llvm.org
Mon Sep 18 09:10:49 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 17a12a27ec1f0e44b4c379cac8fc9536074b4ed4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-09-18 (Mon, 18 Sep 2023)

  Changed paths:
    M llvm/test/CodeGen/RISCV/unaligned-load-store.ll

  Log Message:
  [RISCV] Add test case to show bad codegen for unaligned i64 store of a large constant.

On the first split we create two i32 trunc stores and a srl to shift
the high part down. The srl gets constant folded, but to produce
a new i32 constant. But the truncstore for the low store still uses
the original constant.

This original constant then gets converted to a constant pool
before we revisit the stores to further split them. The constant
pool prevents further constant folding of the additional srls.

After legalization is done, we run DAGCombiner and get some constant
folding of srl via computeKnownBits which can peek through the constant
pool load. This can create new constants that also need a constant pool.

  Commit: 8f04d81ede8900b05c91c56e4db75f3e9a2cce25
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-09-18 (Mon, 18 Sep 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/RISCV/unaligned-load-store.ll

  Log Message:
  [SelectionDAG][RISCV] Mask constants to narrow size in TargetLowering::expandUnalignedStore.

If the SRL for Hi constant folds, but we don't remoe those bits from
the Lo, we can end up with strange constant folding through DAGCombine later.
I've only seen this with constants being lowered to constant pools
during lowering on RISC-V.

Compare: https://github.com/llvm/llvm-project/compare/14882d6b7440...8f04d81ede89

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