[all-commits] [llvm/llvm-project] f71a9e: [SelectionDAG][RISCV][PowerPC][X86] Use TargetCons...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f71a9e8bb7223f3f739458840ffec8ceacf4526c
      https://github.com/llvm/llvm-project/commit/f71a9e8bb7223f3f739458840ffec8ceacf4526c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-09-18 (Mon, 18 Sep 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
    M llvm/lib/Target/X86/X86Instr3DNow.td
    M llvm/lib/Target/X86/X86InstrSSE.td
    M llvm/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll

  Log Message:
  -----------
  [SelectionDAG][RISCV][PowerPC][X86] Use TargetConstant for immediates for ISD::PREFETCH. (#66601)

The intrinsic uses ImmArg so TargetConstant would be consistent
with how other intrinsics are handled.

This hides the constants from type legalization so we can remove
the promotion support.

isel patterns are updated accordingly.