[all-commits] [llvm/llvm-project] 4235bc: [RISCV] Fix `vmsge{u}.vx` lowering by not adding t...

[Kiva via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4235bc0112f7714aec46cbb3c94cee57047c1abd
      https://github.com/llvm/llvm-project/commit/4235bc0112f7714aec46cbb3c94cee57047c1abd
  Author: imkiva <imkiva at islovely.icu>
  Date:   2023-08-25 (Fri, 25 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/test/MC/RISCV/rvv/compare.s

  Log Message:
  -----------
  [RISCV] Fix `vmsge{u}.vx` lowering by not adding the mask operand if `vd == v0`

According to `riscv-v-spec-1.0.pdf` page 52:

> masked va >= x, vd == v0
>   pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
>   expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt

The resulting `vmslt{u}.vx` is not masked. This patch fixes the logic in `RISCVAsmParser`, to make the behavior consistent with the case "masked va >= x, any vd" in the later part of the code, where no mask op is added.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158392