[all-commits] [llvm/llvm-project] 030d33: [TableGen] Rename ResourceCycles and StartAtCycle ...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 030d33409568b2f0ea61116e83fd40ca27ba33ac
      https://github.com/llvm/llvm-project/commit/030d33409568b2f0ea61116e83fd40ca27ba33ac
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-08-24 (Thu, 24 Aug 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineScheduler.h
    M llvm/include/llvm/CodeGen/MachineTraceMetrics.h
    M llvm/include/llvm/MC/MCSchedule.h
    M llvm/include/llvm/MCA/HWEventListener.h
    M llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
    M llvm/include/llvm/MCA/HardwareUnits/Scheduler.h
    M llvm/include/llvm/MCA/Support.h
    M llvm/include/llvm/Target/TargetSchedule.td
    M llvm/lib/CodeGen/MachinePipeliner.cpp
    M llvm/lib/CodeGen/MachineScheduler.cpp
    M llvm/lib/CodeGen/MachineTraceMetrics.cpp
    M llvm/lib/MC/MCSchedule.cpp
    M llvm/lib/MCA/HardwareUnits/ResourceManager.cpp
    M llvm/lib/MCA/HardwareUnits/Scheduler.cpp
    M llvm/lib/MCA/InstrBuilder.cpp
    M llvm/lib/MCA/Stages/ExecuteStage.cpp
    M llvm/lib/MCA/Stages/InstructionTables.cpp
    M llvm/lib/MCA/Support.cpp
    M llvm/lib/Target/AArch64/AArch64SchedA510.td
    M llvm/lib/Target/AArch64/AArch64SchedA53.td
    M llvm/lib/Target/AArch64/AArch64SchedA55.td
    M llvm/lib/Target/AArch64/AArch64SchedA57WriteRes.td
    M llvm/lib/Target/AArch64/AArch64SchedA64FX.td
    M llvm/lib/Target/AArch64/AArch64SchedCyclone.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
    M llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
    M llvm/lib/Target/AArch64/AArch64SchedTSV110.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
    M llvm/lib/Target/AMDGPU/SISchedule.td
    M llvm/lib/Target/ARM/ARMSchedule.td
    M llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td
    M llvm/lib/Target/ARM/ARMScheduleA9.td
    M llvm/lib/Target/ARM/ARMScheduleM55.td
    M llvm/lib/Target/ARM/ARMScheduleR52.td
    M llvm/lib/Target/ARM/ARMScheduleSwift.td
    M llvm/lib/Target/Mips/MipsScheduleGeneric.td
    M llvm/lib/Target/Mips/MipsScheduleP5600.td
    M llvm/lib/Target/PowerPC/PPCScheduleP10.td
    M llvm/lib/Target/PowerPC/PPCScheduleP9.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
    M llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
    M llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
    M llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
    M llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
    M llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
    M llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
    M llvm/lib/Target/X86/X86SchedAlderlakeP.td
    M llvm/lib/Target/X86/X86SchedBroadwell.td
    M llvm/lib/Target/X86/X86SchedHaswell.td
    M llvm/lib/Target/X86/X86SchedIceLake.td
    M llvm/lib/Target/X86/X86SchedSandyBridge.td
    M llvm/lib/Target/X86/X86SchedSapphireRapids.td
    M llvm/lib/Target/X86/X86SchedSkylakeClient.td
    M llvm/lib/Target/X86/X86SchedSkylakeServer.td
    M llvm/lib/Target/X86/X86Schedule.td
    M llvm/lib/Target/X86/X86ScheduleAtom.td
    M llvm/lib/Target/X86/X86ScheduleBdVer2.td
    M llvm/lib/Target/X86/X86ScheduleBtVer2.td
    M llvm/lib/Target/X86/X86ScheduleSLM.td
    M llvm/lib/Target/X86/X86ScheduleZnver1.td
    M llvm/lib/Target/X86/X86ScheduleZnver2.td
    M llvm/lib/Target/X86/X86ScheduleZnver3.td
    M llvm/lib/Target/X86/X86ScheduleZnver4.td
    A llvm/test/TableGen/AcquireAtCycle.td
    R llvm/test/TableGen/StartAtCycle.td
    M llvm/tools/llvm-exegesis/lib/Analysis.cpp
    M llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp
    M llvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp
    M llvm/tools/llvm-mca/Views/ResourcePressureView.cpp
    M llvm/tools/llvm-mca/Views/ResourcePressureView.h
    M llvm/utils/TableGen/SubtargetEmitter.cpp

  Log Message:
  -----------
  [TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics

D150312 added a TODO:

TODO: consider renaming the field `StartAtCycle` and `Cycles` to
`AcquireAtCycle` and `ReleaseAtCycle` respectively, to stress the
fact that resource allocation is now represented as an interval,
relatively to the issue cycle of the instruction.

This patch implements that TODO. This naming clarifies how to use these
fields in the scheduler. In addition it was confusing that `StartAtCycle` was
singular but `Cycles` was plural. This renaming fixes this inconsistency.

Differential Revision: https://reviews.llvm.org/D158568