[all-commits] [llvm/llvm-project] e772c0: [RISCV] Use vmv.v.x if Hi bits are undef when lowe...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e772c0ecd814f69ede559ac856230ae7651c9d0c
      https://github.com/llvm/llvm-project/commit/e772c0ecd814f69ede559ac856230ae7651c9d0c
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-08-24 (Thu, 24 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll

  Log Message:
  -----------
  [RISCV] Use vmv.v.x if Hi bits are undef when lowering splat_vector_parts

When lowering a splat_vector_parts, if the hi bits are undefined then we can
splat the lo bits without having to check if it's going to be sign extended or
not, because those bits will be undefined anyway.

I've handled it for both fixed and scalable vectors, but there's no diff
on the scalable vror tests, since the hi bits aren't combined away to
undef in SimplifyDemanded for scalable vectors. I'm not sure why that is.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158625