[all-commits] [llvm/llvm-project] 2ad50f: [DAGCombiner][RISCV][AArch64][PowerPC] Restrict fo...

Craig Topper via All-commits all-commits at lists.llvm.org
Wed Aug 23 20:35:12 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2ad50f354a2dbd7a1c0ab0ab15723ed48d4a5b7b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-08-23 (Wed, 23 Aug 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/vecreduce-bool.ll
    M llvm/test/CodeGen/PowerPC/setcc-logic.ll
    M llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

  Log Message:
  [DAGCombiner][RISCV][AArch64][PowerPC] Restrict foldAndOrOfSETCC from using SMIN/SMAX where and OR/AND would do.

This removes some diffs created by D153502.

I'm assuming an AND/OR won't be worse than an SMIN/SMAX. For
RISC-V at least, AND/OR can be a shorter encoding than SMIN/SMAX.

It's weird that we have two different functions responsible for
folding logic of setccs, but I'm not ready to try to untangle that.

I'm unclear if the PowerPC chang is a regression or not. It looks
like it might use more registers, but I don't understand PowerPC
register so I'm not sure.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D158292

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