[all-commits] [llvm/llvm-project] 97da41: [mlir][ArmSME] Lower loads/stores of (.Q) 128-bit ...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 97da41418226bb426ae67b1e5b9c0ea3255042f2
      https://github.com/llvm/llvm-project/commit/97da41418226bb426ae67b1e5b9c0ea3255042f2
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2023-08-23 (Wed, 23 Aug 2023)

  Changed paths:
    M mlir/lib/Dialect/ArmSME/Transforms/LegalizeForLLVMExport.cpp
    M mlir/lib/Dialect/ArmSME/Utils/Utils.cpp
    M mlir/test/Dialect/ArmSME/vector-ops-to-llvm.mlir
    A mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-store-128-bit-tile.mlir

  Log Message:
  -----------
  [mlir][ArmSME] Lower loads/stores of (.Q) 128-bit tiles to intrinsics

This follows from D155306.

Loads and stores of 128-bit tiles have been confirmed to work in the
`load-store-128-bit-tile.mlir` integration test. However, there is
currently a bug in QEMU (see: https://gitlab.com/qemu-project/qemu/-/issues/1833)
which means this test produces incorrect results (a patch for this issue
is available but not yet in any released version of QEMU). Until a
fixed version of QEMU is available the integration test is expected to fail.

Reviewed By: c-rhodes, awarzynski

Differential Revision: https://reviews.llvm.org/D158418