[all-commits] [llvm/llvm-project] d9320e: [RISCV][GlobalISel] Select register banks for GPR ...
Craig Topper via All-commits
all-commits at lists.llvm.org
Tue Aug 22 12:40:48 PDT 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: d9320e22d4b5ebcd5f2c400cc774c1d16e335f28
https://github.com/llvm/llvm-project/commit/d9320e22d4b5ebcd5f2c400cc774c1d16e335f28
Author: Craig Topper <craig.topper at sifive.com>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
Log Message:
-----------
[RISCV][GlobalISel] Select register banks for GPR ALU instructions
This patch implements the getInstrMapping hook for RISCVRegisterBankInfo and others in order to correctly select the GPR register bank for operands of ALU instructions, and the associated operations introduced by the legalizer.
Co-authored-by: Lewis Revill <lewis.revill at embecosm.com>
Reviewed By: nitinjohnraj
Differential Revision: https://reviews.llvm.org/D76051
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