[all-commits] [llvm/llvm-project] c3b48e: [RISCV] Match strided loads with reversed indexing...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c3b48ec6ff92c47cd6136ee25360d31952a3adf2
      https://github.com/llvm/llvm-project/commit/c3b48ec6ff92c47cd6136ee25360d31952a3adf2
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-08-22 (Tue, 22 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll

  Log Message:
  -----------
  [RISCV] Match strided loads with reversed indexing sequences

This extends the concat_vector of loads to strided_load transform to handle reversed index pattern. The previous code expected indexing of the form (a0, a1+S, a2+S,...). However, we can also see indexing of the form (a1+S, a2+S, a3+S, .., aS). This form is a strided load starting at address aN + S*(n-1) with stride -S.

Note that this is also fixing what looks to be a bug in the memory location reasoning for forward strided case. A strided load with negative stride access eltsize bytes past base ptr, and then bytes *before* base ptr. (That is, the range should extend from before base ptr to after base ptr.)

Differential Revision: https://reviews.llvm.org/D157886