[all-commits] [llvm/llvm-project] ecb855: [RISCV] Reduce LMUL for vector extracts

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ecb855a5a8c5dd9d46ca85041d7fe987fa73ba7c
      https://github.com/llvm/llvm-project/commit/ecb855a5a8c5dd9d46ca85041d7fe987fa73ba7c
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-08-22 (Tue, 22 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

  Log Message:
  -----------
  [RISCV] Reduce LMUL for vector extracts

If we have a known (or bounded) index which definitely fits in a smaller LMUL register group size, we can reduce the LMUL of the slide and extract instructions. This loosens constraints on register allocation, and allows the hardware to do less work, at the potential cost of some additional VTYPE toggles. In practice, we appear (after prior patches) to do a decent job of eliminating the additional VTYPE toggles in most cases.

Differential Revision: https://reviews.llvm.org/D158460