[all-commits] [llvm/llvm-project] dd0d36: [RISCVInsertVSETVLI] Handle vl-preserve case in ba...

Philip Reames via All-commits all-commits at lists.llvm.org
Mon Aug 21 12:28:45 PDT 2023


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dd0d36d09f39942df1e188d2df3a4f7dcc4b8245
      https://github.com/llvm/llvm-project/commit/dd0d36d09f39942df1e188d2df3a4f7dcc4b8245
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-08-21 (Mon, 21 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

  Log Message:
  -----------
  [RISCVInsertVSETVLI] Handle vl-preserve case in backwards rewrite

This updates the backwards mutation code to handle the case where the previous vset was in vl-preserving (x0, x0) form, but that VL was never used before the next vset which changes the VL. Since this requires writing both VL operands, eliminate the restriction on removing GPR producing vsetv as well. (The register will now be written by the earlier vsetv.)

Differential Revision: https://reviews.llvm.org/D158019




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