[all-commits] [llvm/llvm-project] db158c: [AArch64] Update generic sched model to A510
harviniriawan via All-commits
all-commits at lists.llvm.org
Mon Aug 21 04:25:41 PDT 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: db158c7c830807caeeb0691739c41f1d522029e9
https://github.com/llvm/llvm-project/commit/db158c7c830807caeeb0691739c41f1d522029e9
Author: Harvin Iriawan <harvin.iriawan at arm.com>
Date: 2023-08-21 (Mon, 21 Aug 2023)
Changed paths:
M clang/test/CodeGen/aarch64-ABI-align-packed-assembly.c
M llvm/lib/Target/AArch64/AArch64.td
M llvm/test/Analysis/CostModel/AArch64/vector-select.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2_lse128.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-outline_atomics.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8_1a.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll
M llvm/test/CodeGen/AArch64/GlobalISel/aapcs_vararg_frame.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
M llvm/test/CodeGen/AArch64/GlobalISel/select-bitfield-insert.ll
M llvm/test/CodeGen/AArch64/GlobalISel/stacksave-stackrestore.ll
M llvm/test/CodeGen/AArch64/GlobalISel/store-merging.ll
M llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
M llvm/test/CodeGen/AArch64/a57-csel.ll
M llvm/test/CodeGen/AArch64/aarch64-addv.ll
M llvm/test/CodeGen/AArch64/aarch64-be-bv.ll
M llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-combine-add-sub-mul.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
M llvm/test/CodeGen/AArch64/aarch64-fixup-statepoint-regs-crash.ll
M llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll
M llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll
M llvm/test/CodeGen/AArch64/aarch64-isel-csinc.ll
M llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/aarch64-mops-consecutive.ll
M llvm/test/CodeGen/AArch64/aarch64-mops.ll
M llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
M llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
M llvm/test/CodeGen/AArch64/aarch64-pmull2.ll
M llvm/test/CodeGen/AArch64/aarch64-smull.ll
M llvm/test/CodeGen/AArch64/aarch64-uzp1-combine.ll
M llvm/test/CodeGen/AArch64/aarch64-wide-mul.ll
M llvm/test/CodeGen/AArch64/aarch64_fnmadd.ll
M llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll
M llvm/test/CodeGen/AArch64/abd-combine.ll
M llvm/test/CodeGen/AArch64/active_lane_mask.ll
M llvm/test/CodeGen/AArch64/add-extract.ll
M llvm/test/CodeGen/AArch64/addcarry-crash.ll
M llvm/test/CodeGen/AArch64/addsub-constant-folding.ll
M llvm/test/CodeGen/AArch64/addsub.ll
M llvm/test/CodeGen/AArch64/align-down.ll
M llvm/test/CodeGen/AArch64/and-mask-removal.ll
M llvm/test/CodeGen/AArch64/andorbrcompare.ll
M llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll
M llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
M llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
M llvm/test/CodeGen/AArch64/arm64-addrmode.ll
M llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
M llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll
M llvm/test/CodeGen/AArch64/arm64-cse.ll
M llvm/test/CodeGen/AArch64/arm64-csel.ll
M llvm/test/CodeGen/AArch64/arm64-dup.ll
M llvm/test/CodeGen/AArch64/arm64-fcopysign.ll
M llvm/test/CodeGen/AArch64/arm64-fmadd.ll
M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-no-helper.ll
M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
M llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll
M llvm/test/CodeGen/AArch64/arm64-ld1.ll
M llvm/test/CodeGen/AArch64/arm64-ldp.ll
M llvm/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
M llvm/test/CodeGen/AArch64/arm64-mul.ll
M llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
M llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll
M llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
M llvm/test/CodeGen/AArch64/arm64-non-pow2-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-nvcast.ll
M llvm/test/CodeGen/AArch64/arm64-promote-const-complex-initializers.ll
M llvm/test/CodeGen/AArch64/arm64-register-pairing.ll
M llvm/test/CodeGen/AArch64/arm64-rev.ll
M llvm/test/CodeGen/AArch64/arm64-setcc-int-to-fp-combine.ll
M llvm/test/CodeGen/AArch64/arm64-setcc-swap-infloop.ll
M llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
M llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
M llvm/test/CodeGen/AArch64/arm64-vabs.ll
M llvm/test/CodeGen/AArch64/arm64-vector-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-vhadd.ll
M llvm/test/CodeGen/AArch64/arm64-vmul.ll
M llvm/test/CodeGen/AArch64/arm64-vshift.ll
M llvm/test/CodeGen/AArch64/arm64-xaluo.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/arm64_32-addrs.ll
M llvm/test/CodeGen/AArch64/arm64_32.ll
M llvm/test/CodeGen/AArch64/arm64ec-reservedregs.ll
M llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
M llvm/test/CodeGen/AArch64/atomic-ops-msvc.ll
M llvm/test/CodeGen/AArch64/atomic-ops.ll
M llvm/test/CodeGen/AArch64/bcmp-inline-small.ll
M llvm/test/CodeGen/AArch64/bcmp.ll
M llvm/test/CodeGen/AArch64/bf16-shuffle.ll
M llvm/test/CodeGen/AArch64/bfis-in-loop.ll
M llvm/test/CodeGen/AArch64/bitfield-insert.ll
M llvm/test/CodeGen/AArch64/bool-ext-inc.ll
M llvm/test/CodeGen/AArch64/branch-relax-alignment.ll
M llvm/test/CodeGen/AArch64/branch-relax-bcc.ll
M llvm/test/CodeGen/AArch64/build-one-lane.ll
M llvm/test/CodeGen/AArch64/build-vector-to-extract-subvec-crash.ll
M llvm/test/CodeGen/AArch64/build-vector-two-dup.ll
M llvm/test/CodeGen/AArch64/cgp-usubo.ll
M llvm/test/CodeGen/AArch64/cmp-chains.ll
M llvm/test/CodeGen/AArch64/cmp-select-sign.ll
M llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
M llvm/test/CodeGen/AArch64/combine-andintoload.ll
M llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-contract.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-fast.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-contract.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-add-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-i32-add-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-i32-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-i64-add-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-i64-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-i8-add-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-mixed-cases.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
M llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
M llvm/test/CodeGen/AArch64/cond-br-tuning.ll
M llvm/test/CodeGen/AArch64/consthoist-gep.ll
M llvm/test/CodeGen/AArch64/copyprop.ll
M llvm/test/CodeGen/AArch64/ctpop-nonean.ll
M llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
M llvm/test/CodeGen/AArch64/dag-combine-select.ll
M llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
M llvm/test/CodeGen/AArch64/dag-numsignbits.ll
M llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/AArch64/double_reduct.ll
M llvm/test/CodeGen/AArch64/expand-select.ll
M llvm/test/CodeGen/AArch64/expand-vector-rot.ll
M llvm/test/CodeGen/AArch64/extbinopload.ll
M llvm/test/CodeGen/AArch64/extend_inreg_of_concat_subvectors.ll
M llvm/test/CodeGen/AArch64/extract-bits.ll
M llvm/test/CodeGen/AArch64/extract-lowbits.ll
M llvm/test/CodeGen/AArch64/f16-instructions.ll
M llvm/test/CodeGen/AArch64/fabs.ll
M llvm/test/CodeGen/AArch64/fadd-combines.ll
M llvm/test/CodeGen/AArch64/faddp-half.ll
M llvm/test/CodeGen/AArch64/faddp.ll
M llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
M llvm/test/CodeGen/AArch64/fast-isel-gep.ll
M llvm/test/CodeGen/AArch64/fast-isel-memcpy.ll
M llvm/test/CodeGen/AArch64/fast-isel-shift.ll
M llvm/test/CodeGen/AArch64/fcopysign.ll
M llvm/test/CodeGen/AArch64/fcvt.ll
M llvm/test/CodeGen/AArch64/fcvt_combine.ll
M llvm/test/CodeGen/AArch64/fdiv-combine.ll
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/flags-multiuse.ll
M llvm/test/CodeGen/AArch64/fmaximum-legalization.ll
M llvm/test/CodeGen/AArch64/fminimummaximum.ll
M llvm/test/CodeGen/AArch64/fminmax.ll
M llvm/test/CodeGen/AArch64/fmlal-loreg.ll
M llvm/test/CodeGen/AArch64/fold-csel-cttz-and.ll
M llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
M llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll
M llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
M llvm/test/CodeGen/AArch64/fptrunc.ll
M llvm/test/CodeGen/AArch64/fsqrt.ll
M llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
M llvm/test/CodeGen/AArch64/funnel-shift.ll
M llvm/test/CodeGen/AArch64/global-merge-3.ll
M llvm/test/CodeGen/AArch64/gpr_cttz.ll
M llvm/test/CodeGen/AArch64/half.ll
M llvm/test/CodeGen/AArch64/highextractbitcast.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/i128-math.ll
M llvm/test/CodeGen/AArch64/i128_volatile_load_store.ll
M llvm/test/CodeGen/AArch64/illegal-floating-point-vector-compares.ll
M llvm/test/CodeGen/AArch64/insert-extend.ll
M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
M llvm/test/CodeGen/AArch64/insert-subvector.ll
M llvm/test/CodeGen/AArch64/insertshuffleload.ll
M llvm/test/CodeGen/AArch64/isinf.ll
M llvm/test/CodeGen/AArch64/known-never-nan.ll
M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
M llvm/test/CodeGen/AArch64/load-insert-zero.ll
M llvm/test/CodeGen/AArch64/logic-reassociate.ll
M llvm/test/CodeGen/AArch64/logic-shift.ll
M llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
M llvm/test/CodeGen/AArch64/lowerMUL-newload.ll
M llvm/test/CodeGen/AArch64/machine-combiner-copy.ll
M llvm/test/CodeGen/AArch64/machine-combiner-subadd.ll
M llvm/test/CodeGen/AArch64/machine-combiner-transient.ll
M llvm/test/CodeGen/AArch64/machine-licm-sink-instr.ll
M llvm/test/CodeGen/AArch64/machine-licm-sub-loop.ll
M llvm/test/CodeGen/AArch64/machine_cse_impdef_killflags.ll
M llvm/test/CodeGen/AArch64/madd-combiner.ll
M llvm/test/CodeGen/AArch64/memcpy-scoped-aa.ll
M llvm/test/CodeGen/AArch64/merge-trunc-store.ll
M llvm/test/CodeGen/AArch64/midpoint-int.ll
M llvm/test/CodeGen/AArch64/minmax-of-minmax.ll
M llvm/test/CodeGen/AArch64/minmax.ll
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-fusion-lit.ll
M llvm/test/CodeGen/AArch64/mul_pow2.ll
M llvm/test/CodeGen/AArch64/mulcmle.ll
M llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll
M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
M llvm/test/CodeGen/AArch64/neg-imm.ll
M llvm/test/CodeGen/AArch64/neon-abd.ll
M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
M llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
M llvm/test/CodeGen/AArch64/neon-dotpattern.ll
M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
M llvm/test/CodeGen/AArch64/neon-extadd.ll
M llvm/test/CodeGen/AArch64/neon-extracttruncate.ll
M llvm/test/CodeGen/AArch64/neon-mov.ll
M llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll
M llvm/test/CodeGen/AArch64/neon-rshrn.ll
M llvm/test/CodeGen/AArch64/neon-shift-neg.ll
M llvm/test/CodeGen/AArch64/neon-truncstore.ll
M llvm/test/CodeGen/AArch64/neon-wide-splat.ll
M llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
M llvm/test/CodeGen/AArch64/no-sve-no-neon.ll
M llvm/test/CodeGen/AArch64/nontemporal-load.ll
M llvm/test/CodeGen/AArch64/nontemporal.ll
M llvm/test/CodeGen/AArch64/nzcv-save.ll
M llvm/test/CodeGen/AArch64/overeager_mla_fusing.ll
M llvm/test/CodeGen/AArch64/peephole-and-tst.ll
M llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll
M llvm/test/CodeGen/AArch64/pr-cf624b2.ll
M llvm/test/CodeGen/AArch64/pr58350.ll
M llvm/test/CodeGen/AArch64/pr58516.ll
M llvm/test/CodeGen/AArch64/pr61549.ll
M llvm/test/CodeGen/AArch64/predicated-add-sub.ll
M llvm/test/CodeGen/AArch64/pull-negations-after-concat-of-truncates.ll
M llvm/test/CodeGen/AArch64/ragreedy-csr.ll
M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
M llvm/test/CodeGen/AArch64/rand.ll
M llvm/test/CodeGen/AArch64/rcpc3-sve.ll
M llvm/test/CodeGen/AArch64/reduce-and.ll
M llvm/test/CodeGen/AArch64/reduce-or.ll
M llvm/test/CodeGen/AArch64/reduce-shuffle.ll
M llvm/test/CodeGen/AArch64/reduce-xor.ll
M llvm/test/CodeGen/AArch64/regress-tblgen-chains.ll
M llvm/test/CodeGen/AArch64/rotate-extract.ll
M llvm/test/CodeGen/AArch64/sadd_sat.ll
M llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/sat-add.ll
M llvm/test/CodeGen/AArch64/select-constant-xor.ll
M llvm/test/CodeGen/AArch64/select_const.ll
M llvm/test/CodeGen/AArch64/select_fmf.ll
M llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
M llvm/test/CodeGen/AArch64/setcc-type-mismatch.ll
M llvm/test/CodeGen/AArch64/settag-merge-order.ll
M llvm/test/CodeGen/AArch64/settag-merge.ll
M llvm/test/CodeGen/AArch64/settag.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/shift-amount-mod.ll
M llvm/test/CodeGen/AArch64/shift-by-signext.ll
M llvm/test/CodeGen/AArch64/shift_minsize.ll
M llvm/test/CodeGen/AArch64/shrink-wrap-byval-inalloca-preallocated.ll
M llvm/test/CodeGen/AArch64/shrink-wrapping-vla.ll
M llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
M llvm/test/CodeGen/AArch64/shuffles.ll
M llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
M llvm/test/CodeGen/AArch64/sinksplat.ll
M llvm/test/CodeGen/AArch64/sitofp-fixed-legal.ll
M llvm/test/CodeGen/AArch64/sme-aarch64-svcount.ll
M llvm/test/CodeGen/AArch64/sme-disable-gisel-fisel.ll
M llvm/test/CodeGen/AArch64/sme-intrinsics-loads.ll
M llvm/test/CodeGen/AArch64/sme-intrinsics-mova-extract.ll
M llvm/test/CodeGen/AArch64/sme-intrinsics-mova-insert.ll
M llvm/test/CodeGen/AArch64/sme-intrinsics-stores.ll
M llvm/test/CodeGen/AArch64/sme-lazy-save-call.ll
M llvm/test/CodeGen/AArch64/sme-shared-za-interface.ll
M llvm/test/CodeGen/AArch64/sme-streaming-body.ll
M llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll
M llvm/test/CodeGen/AArch64/sme-streaming-interface.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-insert-mova.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-ld1.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-ldnt1.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlals.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-sub.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-vdot.ll
M llvm/test/CodeGen/AArch64/speculation-hardening-loads.ll
M llvm/test/CodeGen/AArch64/split-vector-insert.ll
M llvm/test/CodeGen/AArch64/sqrt-fastmath.ll
M llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
M llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
M llvm/test/CodeGen/AArch64/sshl_sat.ll
M llvm/test/CodeGen/AArch64/ssub_sat.ll
M llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/stack-guard-sysreg.ll
M llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll
M llvm/test/CodeGen/AArch64/sve-abd.ll
M llvm/test/CodeGen/AArch64/sve-alloca.ll
M llvm/test/CodeGen/AArch64/sve-bitcast.ll
M llvm/test/CodeGen/AArch64/sve-breakdown-scalable-vectortype.ll
M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
M llvm/test/CodeGen/AArch64/sve-doublereduct.ll
M llvm/test/CodeGen/AArch64/sve-expand-div.ll
M llvm/test/CodeGen/AArch64/sve-extract-element.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-fcmp.ll
M llvm/test/CodeGen/AArch64/sve-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve-fix-length-and-combine-512.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-addressing-modes.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-bitcast.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-build-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-compares.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-fma.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-rounding.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp128.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-compares.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-log.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-limit-duplane.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-no-vscale-range.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-stores.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-trunc.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll
M llvm/test/CodeGen/AArch64/sve-fold-vscale.ll
M llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll
M llvm/test/CodeGen/AArch64/sve-fp-combine.ll
M llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
M llvm/test/CodeGen/AArch64/sve-fp-reduce-fadda.ll
M llvm/test/CodeGen/AArch64/sve-fpext-load.ll
M llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
M llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
M llvm/test/CodeGen/AArch64/sve-fptrunc-store.ll
M llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
M llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll
M llvm/test/CodeGen/AArch64/sve-gep.ll
M llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll
M llvm/test/CodeGen/AArch64/sve-insert-element.ll
M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
M llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
M llvm/test/CodeGen/AArch64/sve-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll
M llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-ld1r.ll
M llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter-legalize.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter.ll
M llvm/test/CodeGen/AArch64/sve-pr62151.ll
M llvm/test/CodeGen/AArch64/sve-pred-arith.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
M llvm/test/CodeGen/AArch64/sve-ptest-removal-sink.ll
M llvm/test/CodeGen/AArch64/sve-redundant-store.ll
M llvm/test/CodeGen/AArch64/sve-select.ll
M llvm/test/CodeGen/AArch64/sve-sext-zext.ll
M llvm/test/CodeGen/AArch64/sve-smulo-sdnode.ll
M llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
M llvm/test/CodeGen/AArch64/sve-split-fcvt.ll
M llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
M llvm/test/CodeGen/AArch64/sve-split-int-pred-reduce.ll
M llvm/test/CodeGen/AArch64/sve-split-load.ll
M llvm/test/CodeGen/AArch64/sve-split-store.ll
M llvm/test/CodeGen/AArch64/sve-srem-combine-loop.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-stepvector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll
M llvm/test/CodeGen/AArch64/sve-tailcall.ll
M llvm/test/CodeGen/AArch64/sve-trunc.ll
M llvm/test/CodeGen/AArch64/sve-umulo-sdnode.ll
M llvm/test/CodeGen/AArch64/sve-vecreduce-fold.ll
M llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
M llvm/test/CodeGen/AArch64/sve-vector-splat.ll
M llvm/test/CodeGen/AArch64/sve-vscale-attr.ll
M llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
M llvm/test/CodeGen/AArch64/sve2-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve2-fixed-length-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve2-intrinsics-combine-rshrnb.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx2.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx4.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-stores.ll
M llvm/test/CodeGen/AArch64/swift-return.ll
M llvm/test/CodeGen/AArch64/swifterror.ll
M llvm/test/CodeGen/AArch64/tbl-loops.ll
M llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
M llvm/test/CodeGen/AArch64/typepromotion-overflow.ll
M llvm/test/CodeGen/AArch64/typepromotion-phisret.ll
M llvm/test/CodeGen/AArch64/typepromotion-signed.ll
M llvm/test/CodeGen/AArch64/uadd_sat.ll
M llvm/test/CodeGen/AArch64/uadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-innerouter.ll
M llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-interleavedbits.ll
M llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
M llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-lowhigh.ll
M llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-variablemask.ll
M llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll
M llvm/test/CodeGen/AArch64/urem-lkk.ll
M llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll
M llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll
M llvm/test/CodeGen/AArch64/urem-vector-lkk.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
M llvm/test/CodeGen/AArch64/vcvt-oversize.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-truncate-store.ll
M llvm/test/CodeGen/AArch64/vec-libcalls.ll
M llvm/test/CodeGen/AArch64/vec_cttz.ll
M llvm/test/CodeGen/AArch64/vec_uaddo.ll
M llvm/test/CodeGen/AArch64/vec_umulo.ll
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
M llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmaximum.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fminimum.ll
M llvm/test/CodeGen/AArch64/vector-fcopysign.ll
M llvm/test/CodeGen/AArch64/vector-fcvt.ll
M llvm/test/CodeGen/AArch64/vector-gep.ll
M llvm/test/CodeGen/AArch64/vldn_shuffle.ll
M llvm/test/CodeGen/AArch64/vselect-constants.ll
M llvm/test/CodeGen/AArch64/vselect-ext.ll
M llvm/test/CodeGen/AArch64/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/AArch64/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/AArch64/win64_vararg.ll
M llvm/test/CodeGen/AArch64/win64_vararg2.ll
M llvm/test/CodeGen/AArch64/win64_vararg_float.ll
M llvm/test/CodeGen/AArch64/win64_vararg_float_cc.ll
M llvm/test/CodeGen/AArch64/wineh-bti.ll
M llvm/test/CodeGen/AArch64/zero-call-used-regs.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/CodeGen/AArch64/zext.ll
M llvm/test/MC/AArch64/elf-globaladdress.ll
M llvm/test/MachineVerifier/test_g_concat_vectors.mir
M llvm/test/Transforms/CanonicalizeFreezeInLoops/aarch64.ll
M llvm/test/Transforms/CodeGenPrepare/AArch64/large-offset-gep.ll
M llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-ldp.ll
M llvm/test/Transforms/LoopStrengthReduce/AArch64/pr53625.ll
M llvm/test/Transforms/LoopStrengthReduce/AArch64/small-constant.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected
Log Message:
-----------
[AArch64] Update generic sched model to A510
Refresh of the generic scheduling model to use A510 instead of A55.
Main benefits are to the little core, and introducing SVE scheduling information.
Changes tested on various OoO cores, no performance degradation is seen.
Differential Revision: https://reviews.llvm.org/D156799
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