[all-commits] [llvm/llvm-project] 89b8eb: [LegalizeTypes][RISCV] Correct FP_TO_{S, U}INT expa...

[Alex Bradbury via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 89b8ebf3d68cbecf9e8c889362c793ad4015169a
      https://github.com/llvm/llvm-project/commit/89b8ebf3d68cbecf9e8c889362c793ad4015169a
  Author: Alex Bradbury <asb at igalia.com>
  Date:   2023-08-09 (Wed, 09 Aug 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/RISCV/bfloat-convert.ll

  Log Message:
  -----------
  [LegalizeTypes][RISCV] Correct FP_TO_{S,U}INT expansion when bf16 isn't a legal type

As noted in D156990, the logic in ExpandIntRes_FP_TO_SINT assumes that
if the type action for the float type is TypeSoftPromoteHalf, is must
have been an f16 (half). However, the meaning of that type action has
been overloaded and it is used for both f16 and bf16. This patch adds an
appropriate check to ensure ISD::FP16_TO_FP or ISD::BF16_TO_FP is
emitted as required.

Differential Revision: https://reviews.llvm.org/D157287