[all-commits] [llvm/llvm-project] b16044: Revert "[mlir][VectorOps] Use SCF for vector.print...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b160442dd2ca610d3cfc2085d6f6fa4efdf94ca5
      https://github.com/llvm/llvm-project/commit/b160442dd2ca610d3cfc2085d6f6fa4efdf94ca5
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2023-08-09 (Wed, 09 Aug 2023)

  Changed paths:
    M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
    M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
    M mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
    M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
    M mlir/test/Conversion/VectorToSCF/vector-to-scf.mlir
    M mlir/test/Integration/Dialect/Arith/CPU/test-wide-int-emulation-compare-results-i16.mlir
    M mlir/test/Integration/Dialect/Arith/CPU/test-wide-int-emulation-constants-i16.mlir
    M mlir/test/Integration/Dialect/LLVMIR/CPU/X86/test-inline-asm-vector.mlir
    M mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-sve.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/X86Vector/test-dot.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/X86Vector/test-mask-compress.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/X86Vector/test-rsqrt.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/X86Vector/test-vp2intersect-i32.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-0-d-vectors.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-broadcast.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-compress.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-constant-mask.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-contraction.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-create-mask-v4i1.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-create-mask.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-expand.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-extract-strided-slice.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-flat-transpose-col.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-flat-transpose-row.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-fma.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-gather.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-index-vectors.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-insert-strided-slice.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-maskedload.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-maskedstore.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-matrix-multiply-col.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-matrix-multiply-row.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-outerproduct-f32.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-outerproduct-i64.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-print-fp.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-print-int.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-realloc.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-f32-reassoc.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-f32.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-f64-reassoc.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-f64.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-i32.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-i4.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-i64.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-si4.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-ui4.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-scan.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-scatter.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-shape-cast.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-shuffle.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-shuffle16x16.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-sparse-dot-matvec.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-sparse-saxpy-jagged-matvec.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-transpose.mlir
    M mlir/test/Integration/Dialect/Vector/GPU/CUDA/test-reduction-distribute.mlir
    M mlir/test/Integration/Dialect/Vector/GPU/CUDA/test-warp-distribute.mlir
    M mlir/test/mlir-cpu-runner/math-polynomial-approx.mlir
    M mlir/test/mlir-cpu-runner/test-expand-math-approx.mlir

  Log Message:
  -----------
  Revert "[mlir][VectorOps] Use SCF for vector.print and allow scalable vectors"

This reverts commit 3875804a0725c6490b4c0e76e1c0e1e0dbccedf4.

This caused some test failures for the MLIR python bindings. Reverting
until those are addressed.