[all-commits] [llvm/llvm-project] 40cc10: [RISCV] Scalarize binop followed by extractelement...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 40cc106fa09e543cc12abeab6214012fb46c605b
      https://github.com/llvm/llvm-project/commit/40cc106fa09e543cc12abeab6214012fb46c605b
  Author: Jim Lin <jim at andestech.com>
  Date:   2023-08-03 (Thu, 03 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll

  Log Message:
  -----------
  [RISCV] Scalarize binop followed by extractelement to custom lowered instruction

isOperationLegalOrCustomOrPromote returns true only if VT is other or legal
and operation action is Legal, Custom or Promote.
Permit a vector binary operation can be converted to scalar binary operation which is custom lowered with illegal type.
One of cases is i32 isn't a legal type on RV64 and its ALU operations is set to custom lowering,
so vadd for element type i32 can be converted to addw.

Reviewed By: jacquesguan, craig.topper

Differential Revision: https://reviews.llvm.org/D156692