[all-commits] [llvm/llvm-project] 5ff5da: [RISCV] Add simple DAG combine to pull xor with 1 ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5ff5dac8528ac23a006a1cec250e338c1185499a
      https://github.com/llvm/llvm-project/commit/5ff5dac8528ac23a006a1cec250e338c1185499a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-25 (Tue, 25 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll
    M llvm/test/CodeGen/RISCV/atomic-signext.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/RISCV/condops.ll

  Log Message:
  -----------
  [RISCV] Add simple DAG combine to pull xor with 1 through select_cc.

If we're selecting the result of two setccs that have been legalized
by introducing an xor with 1, we can pull the xor with 1 through the
select to enable more optimizations.

We could generalize this to other binary operators with identical
conditions, but those are usually caught before we legalize the select.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D156144