[all-commits] [llvm/llvm-project] d71329: [RISCV] Add bf16 as a valid type for the FPR16 reg...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d71329773d9ac0ba8cf570dc0d5ad89ce20a00c2
      https://github.com/llvm/llvm-project/commit/d71329773d9ac0ba8cf570dc0d5ad89ce20a00c2
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-17 (Mon, 17 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td

  Log Message:
  -----------
  [RISCV] Add bf16 as a valid type for the FPR16 register class.

This makes it possible for D153234 to use the FPR16 register class
for bf16 instructions.

Differential Revision: https://reviews.llvm.org/D155418