[all-commits] [llvm/llvm-project] 6a35ce: [RISCV][GlobalISel] Legalize add, sub and binary l...
Nitin John Raj via All-commits
all-commits at lists.llvm.org
Fri Jul 14 18:28:31 PDT 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 6a35ceaacf06a5fcaf649d4f63600a79b365e103
https://github.com/llvm/llvm-project/commit/6a35ceaacf06a5fcaf649d4f63600a79b365e103
Author: Nitin John Raj <nitin.raj at sifive.com>
Date: 2023-07-14 (Fri, 14 Jul 2023)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-add.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-and.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-or.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-sub.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-xor.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-and.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-or.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-sub.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-xor.mir
Log Message:
-----------
[RISCV][GlobalISel] Legalize add, sub and binary logical instructions for narrow types
For rv32, we test the legalization of i8, i16 and i32. For rv64, we additionally test the legalization of i64.
This is the first of a series of commits aiming to legalize arithmetic instructions for RISCV.
Reviewed By: craig.topper, arsenm
Differential Revision: https://reviews.llvm.org/D154978
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