[all-commits] [llvm/llvm-project] d3c304: [DWARF] Fix undefined behaviour in dwarf type printer

[Maurice Heumann via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d3c304fd637f1e1d9e311066a299839ace1c9344
      https://github.com/llvm/llvm-project/commit/d3c304fd637f1e1d9e311066a299839ace1c9344
  Author: Maurice Heumann <maurice.heumann at wibu.com>
  Date:   2023-07-14 (Fri, 14 Jul 2023)

  Changed paths:
    M llvm/lib/DebugInfo/DWARF/DWARFTypePrinter.cpp

  Log Message:
  -----------
  [DWARF] Fix undefined behaviour in dwarf type printer

The value to be formatted here, Val, is an int64_t which cannot be
formatted using %x. This commit adjusts all misuses I was able to find
in the llvm-dwarfdump project.

Failing tests in https://reviews.llvm.org/D153800 lead to the discovery
and analysis of this issue.

Differential Revision: https://reviews.llvm.org/D155093


  Commit: a1cdb323e2610a8e9d8f67382c27172f5f3f3511
      https://github.com/llvm/llvm-project/commit/a1cdb323e2610a8e9d8f67382c27172f5f3f3511
  Author: Maurice Heumann <maurice.heumann at wibu.com>
  Date:   2023-07-14 (Fri, 14 Jul 2023)

  Changed paths:
    M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
    M llvm/test/CodeGen/ARM/copy-by-struct-i32.ll
    M llvm/test/CodeGen/ARM/ha-alignstack-call.ll
    M llvm/test/CodeGen/ARM/indexed-mem.ll
    M llvm/test/CodeGen/ARM/prera-ldst-aliasing.mir
    M llvm/test/CodeGen/ARM/prera-ldst-insertpt.mir
    M llvm/test/CodeGen/ARM/vector-DAGCombine.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
    M llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-scatter-ptrs.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-slp.ll
    M llvm/test/CodeGen/Thumb2/mve-vld3.ll
    M llvm/test/CodeGen/Thumb2/mve-vst2.ll
    M llvm/test/CodeGen/Thumb2/postinc-distribute.mir

  Log Message:
  -----------
  [ARM] Adjust strd/ldrd codegen alignment requirements

In change https://reviews.llvm.org/D152790, it was discovered that the
alignment requirement calculation for LDRD/STRD codegen was suboptimal
and the calculation for volatile loads and stores was adjusted.

This change here adopts the calculation for the remaining non-volatile
occurances.

Recommitting after undefined behavior fix in D155093.

Differential Revision: https://reviews.llvm.org/D153800


Compare: https://github.com/llvm/llvm-project/compare/0af663f80da0...a1cdb323e261