[all-commits] [llvm/llvm-project] 3a0a25: [RISCV] Support i32 clmul* intrinsics on RV64.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3a0a25f9b600b3f18810c4287f0f2e4e48cca68e
      https://github.com/llvm/llvm-project/commit/3a0a25f9b600b3f18810c4287f0f2e4e48cca68e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-14 (Fri, 14 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll

  Log Message:
  -----------
  [RISCV] Support i32 clmul* intrinsics on RV64.

We can use an i64 clmul to emulate i32 clmul.
For clmulh and clmulr we need to zero extend the 32 bit input
to 64 bits then extract either bits [63:32] or [62:31].

Unfortunately, without Zba we need to use 2 shifts for the
zero extends. These can be optimized out later if the producing
instruction already zeroed the upper bits or if we can use lwu.

There are alternative sequences we can use for clmulh/clmulr
when the zero extend isn't free, but those are best handled by
a DAG combine to give the best opportunity for removing the extend.

This allows us to implement i32 clmul C intrinsics proposed in
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D154729