[all-commits] [llvm/llvm-project] b159c5: [SystemZ] Use named MI sub-operands

[Ilya Leoshkevich via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b159c5f958f747308987b4d48a2070c9394d3450
      https://github.com/llvm/llvm-project/commit/b159c5f958f747308987b4d48a2070c9394d3450
  Author: Ilya Leoshkevich <iii at linux.ibm.com>
  Date:   2023-07-14 (Fri, 14 Jul 2023)

  Changed paths:
    M llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
    M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
    M llvm/lib/Target/SystemZ/SystemZInstrFormats.td
    M llvm/lib/Target/SystemZ/SystemZInstrInfo.td
    M llvm/lib/Target/SystemZ/SystemZInstrVector.td
    M llvm/lib/Target/SystemZ/SystemZOperands.td
    M llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt
    M llvm/test/MC/Disassembler/SystemZ/insns.txt

  Log Message:
  -----------
  [SystemZ] Use named MI sub-operands

Prepare for removing the MemOpsEmitted workaround for symbolic
displacements by letting TableGen know about the offsets of the
displacement sub-operands within the instruction.

There are alternative ways to do this that were tried and rejected:

- Creating encoders and decoders for each possible displacement offset.
  This is too repetitive.

- Use VarLenCodeEmitter [1]. The resulting diff is quite large.

Instead, use the named sub-operand support introduced by commit
a538d1f13a13 ("[TableGen][CodeEmitterGen] Allow local names for
sub-operands in a operand list.").

Describe instruction encodings in terms of sub-operands instead of
operands (e.g. B, D, L vs BDL) - this also better matches the pictures
from the Principles of Operation. Decompose operands into sub-operands
using the new (bdaddr12only $B1, $D1):$BD1 syntax. Replace the
encoders and the decoders of the operands with these of the
sub-operands.

Since DecodeADDR64BitRegisterClass() is now used for bases and indices,
change it to return NoRegister when decoding 0. This also changes the
disassembly of some instructions, e.g., br %r0 becomes br 0. Since this
better captures the instruction semantics, namely, that the value of
%r0 is not used, keep this change and update the tests.

[1] https://m680x0.github.io/blog/2022/02/varlen-encoder.html

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D155194