[all-commits] [llvm/llvm-project] d212e9: [RISCV] Update test after the addition for roundin...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d212e99bc5144696f95f09a573da6ed0d85601a0
      https://github.com/llvm/llvm-project/commit/d212e99bc5144696f95f09a573da6ed0d85601a0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-13 (Thu, 13 Jul 2023)

  Changed paths:
    M clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c

  Log Message:
  -----------
  [RISCV] Update test after the addition for rounding mode to vfadd intrinsic. NFC

The greediness of the operand matching regular expressions made
the test pass even though an operand is missing.